US 11,056,474 B2
Semiconductor package, semiconductor device and method of forming the same
Chen-Hua Yu, Hsinchu (TW); Chung-Shi Liu, Hsinchu (TW); Chih-Fan Huang, Kaohsiung (TW); Tsai-Tsung Tsai, Taoyuan (TW); Wei-Hung Lin, Xinfeng Township (TW); and Ming-Da Cheng, Jhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 19, 2018, as Appl. No. 16/195,402.
Application 16/195,402 is a continuation of application No. 15/373,719, filed on Dec. 9, 2016, granted, now 10,134,717.
Application 15/373,719 is a continuation of application No. 14/152,168, filed on Jan. 10, 2014, granted, now 9,530,762, issued on Dec. 27, 2016.
Prior Publication US 2019/0088635 A1, Mar. 21, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/18 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 21/561 (2013.01); H01L 23/00 (2013.01); H01L 23/3114 (2013.01); H01L 24/19 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48095 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2924/00 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19105 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a semiconductor package comprising:
providing a temporary bonding layer over a carrier;
providing a chip and a passive component over the temporary bonding layer;
providing a mask layer having a recess formed therein between the chip and the passive component, the mask layer being disposed in a same vertical level as the chip and the passive component, the mask layer being a conformal layer;
providing a molding compound in the recess of the mask layer, a thickness of the molding compound being equal to a height of the recess, top surfaces of the mask layer, the molding compound, the chip, and the passive component being at a same level;
providing a redistribution layer over and connected to the chip and the passive component;
providing a plurality of metal bumps connected to the chip and the passive component by the redistribution layer;
after providing the plurality of metal bumps, debonding the semiconductor package from the carrier; and
providing the semiconductor package over and connected to a printed circuit board.