US 11,056,471 B2
Semiconductor device and method of manufacture
Jing-Cheng Lin, Hsin-Chu (TW); Po-Hao Tsai, Zhongli (TW); Li-Hui Cheng, New Taipei (TW); and Porter Chen, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Dec. 18, 2019, as Appl. No. 16/719,738.
Application 16/719,738 is a continuation of application No. 16/017,351, filed on Jun. 25, 2018, granted, now 10,515,937.
Application 16/017,351 is a continuation of application No. 15/495,494, filed on Apr. 24, 2017, granted, now 10,008,485, issued on Jun. 26, 2018.
Application 15/495,494 is a continuation of application No. 14/555,405, filed on Nov. 26, 2014, granted, now 9,633,934, issued on Apr. 25, 2017.
Prior Publication US 2020/0126959 A1, Apr. 23, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 21/561 (2013.01); H01L 23/49811 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/92 (2013.01); H01L 24/97 (2013.01); H01L 25/50 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/5389 (2013.01); H01L 25/0657 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/119 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/9222 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving an integrated circuit (IC) package that includes:
a mold encapsulating an IC device, a through via structure, and a metal layer disposed over a backside of the IC device, wherein the mold has a first side and a second side that is opposite the first side and the metal layer is a portion of a thermal path for removing heat from the IC device,
a redistribution layer disposed on the first side of the mold, wherein the redistribution layer is coupled to the through via structure and a front side of the IC device, and
a patterned polymer layer disposed on the second side of the mold, wherein the patterned polymer layer has an opening exposing a portion of the metal layer; and
bonding a thermal structure to the metal layer of the IC device via a thermally conductive material that fills the opening of the patterned polymer layer.