US 11,056,440 B2
Methods of manufacturing semiconductor device and semiconductor device
Ying-Hua Chen, Hsinchu (TW); Feng-Jia Shiu, Jhudong Township (TW); and Wen-Chen Lu, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Oct. 3, 2019, as Appl. No. 16/591,961.
Claims priority of provisional application 62/774,135, filed on Nov. 30, 2018.
Prior Publication US 2020/0176390 A1, Jun. 4, 2020
Int. Cl. H01L 23/544 (2006.01); H01L 23/522 (2006.01); H01L 27/22 (2006.01); H01L 21/3105 (2006.01); H01L 21/02 (2006.01); H01L 27/24 (2006.01)
CPC H01L 23/544 (2013.01) [H01L 21/02164 (2013.01); H01L 21/02167 (2013.01); H01L 21/31053 (2013.01); H01L 23/5226 (2013.01); H01L 27/226 (2013.01); H01L 27/2463 (2013.01); H01L 2223/54426 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
forming a first interlayer dielectric (ILD) layer over a substrate;
forming a chemical mechanical polishing (CMP) stop layer over the first ILD layer;
forming a trench opening by patterning the CMP stop layer and the first ILD layer;
forming an underlying first process mark by forming a first conductive layer in the trench opening;
forming a lower dielectric layer over the underlying first process mark;
forming a middle dielectric layer over the lower dielectric layer;
forming an upper dielectric layer over the middle dielectric layer;
performing a planarization operation on the upper, middle and lower dielectric layers so that a part of the middle dielectric layer remains over the underlying first process mark; and
forming a second process mark by the lower dielectric layer by removing the remaining part of the middle dielectric layer.