US 11,056,438 B2
Semiconductor packages and method of forming the same
Ming-Fa Chen, Taichung (TW); Nien-Fang Wu, Chiayi (TW); Sung-Feng Yeh, Taipei (TW); Tzuan-Horng Liu, Taoyuan (TW); and Chao-Wen Shih, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Oct. 20, 2019, as Appl. No. 16/658,131.
Claims priority of provisional application 62/867,855, filed on Jun. 27, 2019.
Prior Publication US 2020/0411445 A1, Dec. 31, 2020
Int. Cl. H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/214 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19105 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first die;
a second die bonded to the first die;
a through via, disposed aside the second die and electrically connected to the first die, the through via comprising a first portion having a first width and a second portion having a second width different from the first width, the second portion disposed between the first portion and the first die, wherein the first portion comprises a first seed layer and a first conductive layer, the second portion comprises a second seed layer and a second conductive layer, the first seed layer is disposed aside an interface between the first conductive layer and the second conductive layer, and the second seed layer is disposed between the second conductive layer and the dielectric encapsulation and between the second conductive layer and the first die; and
a dielectric encapsulation, encapsulating the second die and the through via.