US 11,056,433 B2
Redistribution layer structures for integrated circuit package
Jie Chen, New Taipei (TW); Ying-Ju Chen, Yunlin County (TW); Hsien-Wei Chen, Hsinchu (TW); Der-Chyang Yeh, Hsinchu (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 26, 2020, as Appl. No. 16/883,210.
Application 16/520,435 is a division of application No. 15/684,224, filed on Aug. 23, 2017, granted, now 10,366,953, issued on Jul. 30, 2019.
Application 16/883,210 is a continuation of application No. 16/520,435, filed on Jul. 24, 2019, granted, now 10,665,540.
Claims priority of provisional application 62/430,223, filed on Dec. 5, 2016.
Prior Publication US 2020/0286830 A1, Sep. 10, 2020
Int. Cl. H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H01L 23/522 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01)
CPC H01L 23/5283 (2013.01) [H01L 23/5226 (2013.01); H01L 24/02 (2013.01); H01L 24/16 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 24/96 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 2224/0233 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/24147 (2013.01); H01L 2224/25171 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73209 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3512 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package, comprising:
an IC die having a first conductive via, wherein the first conductive via has a peripheral edge; and
a routing structure having a second conductive via and a conductive structure, wherein the second conductive via couples the conductive structure to the first conductive via, wherein the conductive structure comprises:
a cap region overlapping an area of the first conductive via;
a routing region having a first width from a top-down view; and
an intermediate region having a second width from the top-down view along the peripheral edge of the first conductive via and arranged to couple the cap region to the routing region, the second width being greater than the first width.