US 11,056,427 B2
Chip package
Kuei-Wei Chen, Taoyuan (TW); and Chia-Ming Cheng, New Taipei (TW)
Assigned to XINTEC INC., Taoyuan (TW)
Filed by XINTEC INC., Taoyuan (TW)
Filed on Sep. 19, 2019, as Appl. No. 16/576,714.
Claims priority of application No. 201811169457.X (CN), filed on Oct. 8, 2018.
Prior Publication US 2020/0111737 A1, Apr. 9, 2020
Int. Cl. H01L 23/522 (2006.01); H01L 23/48 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 23/481 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A chip package, comprising:
a substrate;
a first dielectric layer located on a lower surface of the substrate;
a first metal layer located on a lower surface of the first dielectric layer and having a plurality of first sections, wherein every two adjacent first sections have a gap therebetween;
a second dielectric layer located on a lower surface of the first metal layer and the lower surface of the first dielectric layer;
a second metal layer located on a lower surface of the second dielectric layer and having a plurality of second sections, wherein the second sections are respectively aligned with the gaps, and two sides of each of the second sections respectively overlap two adjacent first sections;
a plurality of first conductive vias located in the second dielectric layer, wherein each of the first conductive vias is in electrical contact with one of the first sections and one of the second sections; and
a redistribution layer extending from an upper surface of the substrate to the second sections of the second metal layer, wherein the redistribution layer is in direct contact with the first sections of the first metal layer, the first conductive vias, and the second sections of the second metal layer.