US 11,056,407 B2
Semiconductor chips including through electrodes and methods of testing the through electrodes
Sun Myung Choi, Seoul (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Aug. 14, 2019, as Appl. No. 16/540,661.
Claims priority of application No. 10-2019-0025320 (KR), filed on Mar. 5, 2019.
Prior Publication US 2020/0286798 A1, Sep. 10, 2020
Int. Cl. G01R 31/26 (2020.01); G11C 29/44 (2006.01); H01L 23/52 (2006.01); H01L 23/58 (2006.01); H01L 21/66 (2006.01); H01L 23/48 (2006.01); G11C 29/02 (2006.01); G01R 31/3185 (2006.01); G11C 5/04 (2006.01); G11C 5/02 (2006.01)
CPC H01L 22/34 (2013.01) [H01L 22/32 (2013.01); H01L 23/481 (2013.01); G01R 31/318513 (2013.01); G11C 5/02 (2013.01); G11C 5/04 (2013.01); G11C 29/025 (2013.01); H01L 2224/16 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor chip comprising:
a first semiconductor device; and
a second semiconductor device stacked over the first semiconductor device and electrically connected to the first semiconductor device via a plurality of through electrodes,
wherein in a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes, configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally, and
wherein the detection signal indicates that the plurality of through electrodes operated normally when the detection signal is a toggling signal; and
wherein the detection signal indicates that the plurality of through electrodes operated abnormally, by generating an incorrect logic level, when the detection signal has a fixed logic level.