US 11,056,400 B2
Semiconductor device and method
Chao-Ching Cheng, Hsinchu (TW); Tzu-Chiang Chen, Hsinchu (TW); Chen-Feng Hsu, Hsinchu (TW); Yu-Lin Yang, Baoshan Township (TW); Tung Ying Lee, Hsinchu (TW); and Chih Chieh Yeh, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Oct. 11, 2019, as Appl. No. 16/599,840.
Application 16/599,840 is a continuation of application No. 16/417,341, filed on May 20, 2019, granted, now 10,672,667.
Application 16/417,341 is a continuation of application No. 15/864,793, filed on Jan. 8, 2018, granted, now 10,297,508, issued on May 21, 2019.
Claims priority of provisional application 62/552,737, filed on Aug. 31, 2017.
Prior Publication US 2020/0043803 A1, Feb. 6, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/82 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/775 (2006.01); H01L 29/08 (2006.01); H01L 21/8234 (2006.01); B82Y 10/00 (2011.01)
CPC H01L 21/823807 (2013.01) [B82Y 10/00 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/30604 (2013.01); H01L 21/823412 (2013.01); H01L 21/823814 (2013.01); H01L 27/092 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66772 (2013.01); H01L 29/775 (2013.01); H01L 29/78651 (2013.01); H01L 29/78654 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01); H01L 21/823456 (2013.01)] 20 Claims
OG exemplary drawing
 
14. A semiconductor device comprising:
a substrate;
a first source/drain region and a second source/drain region over the substrate;
a first nanowire and a second nanowire disposed between the first source/drain region and the second source/drain region, the first nanowire and the second nanowire comprising a same semiconductor material, the first nanowire extending further from the substrate than the second nanowire;
a gate dielectric material around the first nanowire and around the second nanowire, the gate dielectric material extending continuously from the first nanowire to the second nanowire;
an inner spacer between the first nanowire and the second nanowire, and between the first source/drain region and the gate dielectric material;
a gate material around the gate dielectric material; and
a semiconductor fin over the substrate and laterally adjacent to the first nanowire and the second nanowire, wherein the semiconductor fin extends further from the substrate than the first nanowire, wherein the gate dielectric material is disposed over an upper surface of the semiconductor fin distal to the substrate, and wherein the gate material is disposed over the gate dielectric material.