US 11,056,396 B1
Gate-all-around devices having gate dielectric layers of varying thicknesses and method of forming the same
Pei-Hsun Wu, Hsinchu (TW); Ming-Hung Han, Hsinchu (TW); Po-Nien Chen, Miaoli County (TW); and Chih-Yung Lin, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Dec. 27, 2019, as Appl. No. 16/728,154.
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01)
CPC H01L 21/823462 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/1037 (2013.01); H01L 29/42376 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7854 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a substrate having a first region and a second region;
a first gate-all-around (GAA) device located in the first region, the first GAA device including:
a first channel member extending longitudinally in a first direction;
a first gate structure wrapping a channel region of the first channel member, the first gate structure including a first interfacial layer, the first interfacial layer having a first thickness measured in a second direction generally perpendicular to the first direction;
a second GAA device located in the first region, the second GAA device including:
a second channel member extending longitudinally in the first direction; and
a second gate structure wrapping a channel region of the second channel member, the second gate structure including a second interfacial layer, the second interfacial layer having a second thickness measured in the second direction, the second thickness being greater than the first thickness; and
a third GAA device located in the second region, the third GAA device including:
a third channel member extending longitudinally in the first direction; and
a third gate structure wrapping a channel region of the third channel member, the third gate structure including a third interfacial layer, the third interfacial layer having a third thickness measured in the second direction, the third thickness being greater than the second thickness.
 
16. A method, comprising:
providing a structure having a first channel member, a second channel member, and a third channel member, wherein the first channel member and the second channel member are located in a core region of an integrated circuit device, and the third channel member is located in an input/output (I/O) region of the integrated circuit device;
forming, by a first process, a first oxide layer and a second oxide layer, the first oxide layer wrapping a channel region of the first channel member, the second oxide layer wrapping a channel region of the second channel member;
forming, by a second process different from the first process, a third oxide layer wrapping a channel region of the third channel member;
forming a first dielectric layer, a second dielectric layer, and a third dielectric layer over the first oxide layer, the second oxide layer, and the third oxide layer, respectively;
forming a first capping layer, a second capping layer, and a third capping layer over the first dielectric layer, the second dielectric layer, and the third dielectric layer, respectively;
removing the second capping layer to expose the second dielectric layer, wherein the first capping layer and the third capping layer respectively remain over the first dielectric layer and the third dielectric layer after the removing of the second capping layer; and
after removing the second capping layer, performing an annealing process to increase a thickness of the second oxide layer.