US 11,056,395 B2
Transistor metal gate and method of manufacture
Chung-Chiang Wu, Taichung (TW); Hung-Chin Chung, Pingzhen (TW); Hsien-Ming Lee, Changhua (TW); Chien-Hao Chen, Chuangwei Township (TW); and Ching-Hwanq Su, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 23, 2019, as Appl. No. 16/549,195.
Prior Publication US 2021/0057280 A1, Feb. 25, 2021
Int. Cl. H01L 21/8234 (2006.01); H01L 27/088 (2006.01)
CPC H01L 21/82345 (2013.01) [H01L 21/823456 (2013.01); H01L 27/0886 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a gate dielectric over a first region, a second region, and a third region;
depositing a first metal material over the first region, the second region, and the third region;
depositing a first work function layer over the first region, the second region, and the third region;
forming a first capping layer over the first region, the second region, and the third region on the first work function layer, the first capping layer comprising an insulating material;
removing the first capping layer from the second region;
removing the first capping layer and the first work function layer from the first region; and
depositing a fill material over the first region, the second region, and the third region after the removing the first work function layer from the first region.