US 11,056,183 B2
Multi-port memory circuitry
Yew Keong Chong, Austin, TX (US); Andy Wangkun Chen, Austin, TX (US); and Sriram Thyagarajan, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Apr. 24, 2018, as Appl. No. 15/961,862.
Prior Publication US 2019/0325950 A1, Oct. 24, 2019
Int. Cl. G11C 7/10 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01); H01L 27/11 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/418 (2013.01); G11C 7/1075 (2013.01); H01L 27/11 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
multiple bitcell arrays including a first bitcell array and a second bitcell array that is separate from the first bitcell array, wherein each bitcell in the multiple bitcell arrays has a single write port and a single read port;
multiple input ports including a single write input port for the multiple bitcell arrays and multiple read input ports for the multiple bitcell arrays; and
multiple read output ports for the multiple bitcell arrays,
wherein the single write input port is used for writing data to the first bitcell array or the second bitcell array, and
wherein the multiple read input ports have a first read input port used for reading data from the first bitcell array and a second read input port used for reading data from the second bitcell array.