US 11,056,182 B2
Word line pulse width control circuit in static random access memory
Anjana Singh, Hsinchu (TW); Cheng Hung Lee, Hsinchu (TW); Hau-Tai Shieh, Hsinchu (TW); and Yi-Tzu Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on May 15, 2020, as Appl. No. 16/874,789.
Application 16/874,789 is a continuation of application No. 15/969,834, filed on May 3, 2018, granted, now 10,658,026.
Claims priority of provisional application 62/511,537, filed on May 26, 2017.
Prior Publication US 2020/0279603 A1, Sep. 3, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 8/08 (2006.01); G11C 11/418 (2006.01)
CPC G11C 11/418 (2013.01) [G11C 8/08 (2013.01)] 20 Claims
OG exemplary drawing
1. A control circuit for minimizing a static noise margin of a static random access memory device comprising:
a first transistor;
an inverter coupled to the first transistor; and
a second transistor comprising a gate, a first source/drain terminal and a second source/drain terminal, the second transistor being coupled to the inverter and the first source/drain terminal of the second transistor being coupled in series to the first transistor, and wherein the second source/drain terminal is coupled to a decoder driver circuit,
wherein the second transistor is configured to charge a load of a common decoder line coupled to the first transistor and the second transistor so as to reduce an effective load of the decoder driver circuit.