US 11,056,166 B2
Performing a refresh operation based on a characteristic of a memory sub-system
Tingjun Xie, Milpitas, CA (US); Seungjune Jeon, Santa Clara, CA (US); Zhengang Chen, San Jose, CA (US); Zhenlei Shen, Milpitas, CA (US); and Charles See Yeung Kwong, Redwood City, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 17, 2019, as Appl. No. 16/514,840.
Prior Publication US 2021/0020229 A1, Jan. 21, 2021
Int. Cl. G11C 7/00 (2006.01); G11C 11/406 (2006.01); G11C 11/16 (2006.01)
CPC G11C 11/40607 (2013.01) [G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/40626 (2013.01)] 20 Claims
OG exemplary drawing
 
15. A system comprising:
a memory component; and
a processing device, operatively coupled with the memory component, to:
perform a refresh operation at a memory sub-system, the refresh operation being performed at a current frequency;
receive an error condition associated with the memory sub-system, the error condition corresponding to at least one of a bit error rate or a read-retry trigger rate;
determine whether the error condition associated with the memory sub-system satisfies an error condition threshold; and
in response to determining that the error condition associated with the memory sub-system satisfies the error condition threshold, perform the refresh operation at a different frequency relative to the current frequency.