US 11,056,162 B2
Memory device and method of operating the same
Mi Sun Yoon, Gyeonggi-do (KR); and Dong Hyuk Chae, Seoul (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Apr. 24, 2020, as Appl. No. 16/857,877.
Claims priority of application No. 10-2019-0158488 (KR), filed on Dec. 2, 2019.
Prior Publication US 2021/0166741 A1, Jun. 3, 2021
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01); G11C 7/06 (2006.01)
CPC G11C 7/12 (2013.01) [G11C 7/065 (2013.01); G11C 7/106 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/1087 (2013.01); G11C 7/22 (2013.01)] 20 Claims
OG exemplary drawing
1. A memory device, comprising:
a memory cell array including a plurality of memory cells;
page buffers coupled to the memory cell array through respective bit lines; and
a control logic configured to control so that, during a read operation, data stored in the memory cell array is sensed and stored in the page buffers, and the data stored in the page buffers is output to an external device,
wherein the control logic controls a time point at which a discharge operation is to be performed after the sensing of the data, and a time point at which a data transfer operation between latches included in each of the page buffers is to be performed, in response to a read command received from the external device.