US 11,056,160 B2
Non-volatile memory with selectable hard write
Richard Eguchi, Austin, TX (US); Jon Scott Choy, Austin, TX (US); Anirban Roy, Austin, TX (US); Jacob Williams, Austin, TX (US); and Kerry Ilgenstein, Austin, TX (US)
Assigned to NXP USA, INC., Austin, TX (US)
Filed by NXP USA, INC., Austin, TX (US)
Filed on Oct. 22, 2019, as Appl. No. 16/660,108.
Prior Publication US 2021/0118475 A1, Apr. 22, 2021
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01); G06F 11/10 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01)
CPC G11C 7/1096 (2013.01) [G06F 11/1068 (2013.01); G11C 7/1069 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01)] 20 Claims
OG exemplary drawing
 
17. A method in a non-volatile memory circuit having a memory array with non-volatile memory cells and having a hard write memory, the method comprising:
performing a write operation to an addressed memory location of the memory array, wherein performing the write operation includes:
determining if at least one cell of the addressed memory location is indicated as write error prone in the hard write memory;
if at least one cell is indicated as write error prone in the hard write memory, completing the write operation by performing a hard write of the at least one cell while simultaneously performing a normal write of remaining cells of the addressed memory location of the memory array; and
if at least one cell of the addressed memory location is not indicated as write error prone in the hard write memory, completing the write operation by performing a normal write of all cells of the addressed memory location.