US 11,055,462 B2
Method for generating an electronic circuit modelling substrate coupling effects in an integrated circuit
Ramy Iskander, Paris (FR); Hao Zou, Villejuif (FR); and Yasser Moursy, L'Hay-les-Roses (FR)
Assigned to SORBONNE UNIVERSITE, Paris (FR); and CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, Paris (FR)
Appl. No. 15/739,908
Filed by UNIVERSITÉ PIERRE ET MARIE CURIE, Paris (FR); and CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, Paris (FR)
PCT Filed Jun. 24, 2016, PCT No. PCT/EP2016/064711
§ 371(c)(1), (2) Date Dec. 26, 2017,
PCT Pub. No. WO2016/207374, PCT Pub. Date Dec. 29, 2016.
Claims priority of application No. 15306016 (EP), filed on Jun. 26, 2015.
Prior Publication US 2018/0189436 A1, Jul. 5, 2018
Int. Cl. G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 119/10 (2020.01)
CPC G06F 30/367 (2020.01) [G06F 30/398 (2020.01); G06F 2119/10 (2020.01)] 8 Claims
OG exemplary drawing
 
1. A method for generating an electrical circuit that includes at least a network of diodes, resistors and/or homojunctions, the electrical circuit modelling parasitic effects in a substrate of an integrated circuit that includes electronic devices, the integrated circuit being defined by a set of mask layer layouts and a technology rules file, the method comprising:
generating a simplified 3D layout of the integrated circuit from the set of mask layer layouts and the technology rules file by using only mask layers associated to technology layers involved in the parasitic effects;
defining in the 3D simplified layout a plurality of internal regions, each internal region corresponding to one electronic device of the integrated circuit and one external region corresponding to the part of the simplified 3D layout not included in any internal region;
computing in parallel and independently:
for each internal region, a 3D matrix of adjacent rectangular cuboids, such that there is a limit between at least two adjacent rectangular cuboids where there is a change of doping type or where there is a change of doping concentration in the simplified layout;
for the external region, a mesh of adjacent rectangular cuboids with no overlap and no gap;
extracting a parasitic component with two terminals between each pair of adjacent cuboids, each terminal being positioned at the center of one of the two adjacent cuboids, wherein:
if the two adjacent cuboids have two different doping types, defining the parasitic component as a diode; or
if the two adjacent cuboids have the same doping type with the same doping concentration, defining the parasitic component as a resistor; or
if the two adjacent cuboids have the same doping type and different concentrations, defining the parasitic component as a homojunction; and
defining the electrical characteristics of each parasitic component based on the geometry of the adjacent cuboids and the technological parameters;
connecting all extracted parasitic components into an electrical circuit by considering each rectangular cuboid center as a node of the parasitic component network;
applying a set of xyz coordinates onto the simplified 3D layout, where x and y coordinates define horizontal planes and z coordinate define the integrated circuit depth; and
computing the 3D matrix of internal region by:
scanning the mask layers for finding and collecting corner points of change in the doping type or the doping concentration;
flattening corner points to xy coordinates so that an horizontal rectangular tessellation is built in which each corner point is a corner of at least one rectangle; and
constructing layers of rectangular cuboids by projecting the rectangular tessellation on the z axis, each layer depth corresponding to the depth of at least one corner point.