US 11,055,456 B2
High-level synthesis (HLS) method and apparatus to specify pipeline and spatial parallelism in computer hardware
Jongsok Choi, Toronto (CA); Ruolong Lian, Toronto (CA); Andrew Christopher Canis, Toronto (CA); and Jason Helge Anderson, Toronto (CA)
Assigned to MICROCHIP TECHNOLOGY INC., Chandler, AZ (US)
Filed by LegUp Computing Inc., Toronto (CA)
Filed on Dec. 13, 2019, as Appl. No. 16/714,571.
Application 16/714,571 is a continuation of application No. 15/977,874, filed on May 11, 2018, granted, now 10,579,762.
Claims priority of provisional application 62/506,461, filed on May 15, 2017.
Prior Publication US 2020/0117844 A1, Apr. 16, 2020
Int. Cl. G06F 30/327 (2020.01); G06F 13/16 (2006.01); G06F 30/3312 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 13/1673 (2013.01); G06F 30/3312 (2020.01)] 12 Claims
OG exemplary drawing
 
1. A computer-implemented method for synthesizing a digital circuit, comprising:
receiving a multi-threaded software program with at least one Pthread;
generating a register-transfer level (RTL) hardware description of the at least one Pthread; and
automatically inferring generation of parallel hardware RTL in response to receiving the at least one Pthread.