US 11,055,252 B1
Modular hardware acceleration device
Kypros Constantinides, Seattle, WA (US); and Darin Lee Frink, Lake Tapps, WA (US)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Feb. 1, 2016, as Appl. No. 15/12,409.
Int. Cl. G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 1/18 (2006.01)
CPC G06F 13/4068 (2013.01) [G06F 13/4282 (2013.01); G06F 1/185 (2013.01); G06F 13/4027 (2013.01)] 18 Claims
OG exemplary drawing
 
5. A modular hardware acceleration device, comprising:
a chassis configured to mount in a rack;
a multi-port connection device mounted in the chassis;
a set of hardware accelerators mounted in the chassis;
a set of connectors within the chassis that connect the hardware accelerators to the multi-port connection device, wherein respective ones of the hardware accelerators of the set of hardware accelerators are communicatively coupled to the multi-port connection device via respective ones of the connectors in the chassis;
external ports coupled to the chassis; and
a set of connectors within the chassis that connect the multi-port connection device to the external ports, wherein the respective ones of the external ports are communicatively coupled to the multi-port connection device via respective ones of the connectors in the chassis, wherein the modular hardware acceleration device is configured to couple with an additional modular hardware acceleration device via one or more of the external ports coupled to the chassis and is configured to couple with a modular controller via one or more other ones of the external ports, to form a processing system comprising multiple sets of hardware accelerators, wherein the sets of hardware accelerators of the modular hardware acceleration device are configured to be controlled by the modular controller;
and wherein the modular hardware acceleration device is also configured to be coupled to two other modular hardware acceleration devices, via the external ports, to form a processing system comprising three sets of hardware accelerators of three hardware acceleration devices.