US 11,055,247 B2
System and method to enable fairness on multi-level arbitrations for switch architectures
Gaspar Mora Porta, Campbell, CA (US); Michael A Parker, San Jose, CA (US); Roberto Penaranda Cebrian, Santa Clara, CA (US); Albert S Cheng, Bellevue, WA (US); and Francesc Guim Bernat, Barcelona (ES)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 16/473,561
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Dec. 30, 2016, PCT No. PCT/IB2016/058098
§ 371(c)(1), (2) Date Jun. 25, 2019,
PCT Pub. No. WO2018/122583, PCT Pub. Date Jul. 5, 2018.
Prior Publication US 2020/0050569 A1, Feb. 13, 2020
Int. Cl. G06F 13/40 (2006.01); G06F 13/366 (2006.01); H04L 12/801 (2013.01); H04L 12/937 (2013.01)
CPC G06F 13/4022 (2013.01) [G06F 13/366 (2013.01); H04L 47/10 (2013.01); H04L 49/254 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A switch comprising:
first flow counter circuitry associated with a first input port, the first flow counter circuitry to count input streams flowing through the first input port to generate input stream counts;
second flow counter circuitry associated with a second input port, the second flow counter circuitry to count input streams flowing through the second input port; and
a weighted arbiter circuitry to pass input streams from at least one of the first input port or the second input port to an output port based on a weight derived from the input stream counts from the first flow counter circuitry and input stream counts from the second flow counter circuitry, the input stream counts from the at least one of the first flow counter circuitry or the second flow counter circuitry adjusted, after at least one of the input streams from the at least one of the first flow counter circuitry or the second flow counter circuitry has been passed, dependent on a mode within the switch.