US 11,055,241 B2
Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver
Yueh-Chuan Lu, Hsinchu County (TW); and Ching-Hsiang Chang, Taipei (TW)
Assigned to M31 TECHNOLOGY CORPORATION, Hsinchu County (TW)
Filed by M31 TECHNOLOGY CORPORATION, Hsinchu County (TW)
Filed on Aug. 1, 2019, as Appl. No. 16/529,575.
Application 16/529,575 is a continuation in part of application No. 15/805,098, filed on Nov. 6, 2017, granted, now 10,387,360.
Prior Publication US 2019/0354495 A1, Nov. 21, 2019
Int. Cl. G06F 13/20 (2006.01); G06F 1/10 (2006.01)
CPC G06F 13/20 (2013.01) [G06F 1/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit in a physical layer of a receiver, the integrated circuit comprising:
a multi-lane interface having N lanes, N being an integer greater than one;
a lane selection circuit, coupled to the multi-lane interface, the lane selection circuit being configured to select M of the N lanes as M clock lanes, and output M signals on the M clock lanes respectively, wherein M is a positive integer less than N, and remaining (N−M) lanes serve as (N−M) data lanes; and
N sampling circuits, coupled to the multi-lane interface and the lane selection circuit, wherein (N−M) of the N sampling circuits are coupled to the (N−M) data lanes respectively; each of the (N−M) sampling circuits is configured to sample a signal on one of the (N−M) data lanes according to one of the M signals on the M clock lanes;
wherein the lane selection circuit comprises:
a first selection stage, coupled to the multi-lane interface, the first selection stage being configured to select M of the N lanes as M clock lanes according to one or more first clock select signals; and
a second selection stage, disposed between the first selection stage and the N sampling circuits, the second selection stage being configured to receive the M signals on the M clock lanes, and distribute one of the M signals to one or more of the N sampling circuits according to a second clock select signal different from the one or more first clock select signals.