US 11,055,214 B2
Memory controller and method having predictive buffering of address mapping table
Yen-Chung Chen, Zhubei (TW); Jiunn-Jong Pan, Zhubei (TW); Wei-Ren Hsu, Taipei (TW); and Yi-Ting Wei, Taipei (TW)
Assigned to RAYMX MICROELECTRONICS, CORP., Anhui Province (CN)
Filed by RayMX Microelectronics, Corp., Anhui province (CN)
Filed on Jun. 6, 2019, as Appl. No. 16/433,145.
Claims priority of application No. 107130625 (TW), filed on Aug. 31, 2018.
Prior Publication US 2020/0073794 A1, Mar. 5, 2020
Int. Cl. G06F 12/02 (2006.01); G11C 16/10 (2006.01); G06F 12/1009 (2016.01)
CPC G06F 12/0246 (2013.01) [G06F 12/1009 (2013.01); G11C 16/102 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/7201 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory controller configured to receive a first read command and a second read command from a host device, the memory controller, comprising:
an artificial intelligence (AI) module, to generate an auxiliary command according to the first read command and at least one decision logic; and
a microprocessor, coupled to the AI module, to select a first logical address to physical address mapping table (L2P mapping table) according to a logical address included in the first read command, and to refer to the first L2P mapping table to read data from a memory module;
a buffer memory, coupled to the microprocessor, storing a second L2P mapping table from the memory module in direct response to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the first read command, wherein the second L2P mapping table is buffered in the buffer memory before the memory controller receives the second read command, wherein the second read command is a consecutive read command to the first read command, with respect to a command ordering.