US 11,055,174 B2
Soft chipkill recovery for bitline failures
Naveen Kumar, San Jose, CA (US); Chenrong Xiong, San Jose, CA (US); Aman Bhatia, San Jose, CA (US); Yu Cai, San Jose, CA (US); and Fan Zhang, San Jose, CA (US)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 17, 2019, as Appl. No. 16/717,857.
Claims priority of provisional application 62/787,158, filed on Dec. 31, 2018.
Prior Publication US 2020/0210286 A1, Jul. 2, 2020
Int. Cl. G06F 11/10 (2006.01); H03M 13/45 (2006.01); H03M 13/11 (2006.01)
CPC G06F 11/1068 (2013.01) [H03M 13/1102 (2013.01); H03M 13/45 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for improving performance of a block of a memory device, comprising:
receiving, by a memory controller of the memory device, N codewords of a memory block including Nb codewords, wherein N and Nb are positive integers, Nb is greater than two, Nb is less than N, each codeword corresponding to a memory wordline and each of the Nb codewords comprising an error indication;
decoding, by a decoder, the N codewords;
identifying a first set of codewords that decoded incorrectly and a second set of codewords that decoded correctly;
obtaining channel information for the first set of codewords that decoded incorrectly, the channel information being associated with a parity check portion of each of the first set of codewords;
generating, based on the channel information and decoding results for the second set of codewords that decoded correctly, soft information corresponding to the Nb codewords, the soft information for at least one symbol of the Nb codewords comprising a symbol decision and a probability associated with the symbol decision;
identifying, based on the soft information, a candidate bitline that is likely to have experienced a bitline failure;
updating the soft information corresponding to the candidate bitline; and
performing a decoding operation on the Nb codewords.