US 11,055,023 B2
Electronic device, related controller circuit and method
Shih-Fu Huang, Taoyuan (TW); Yi-Lin Hsieh, Changhua County (TW); and Cheng-Yu Chen, New Taipei (TW)
Assigned to RAYMX MICROELECTRONICS CORP., Hefei (CN)
Filed by RAYMX Microelectronics Corp., Hefei (CN)
Filed on Apr. 23, 2019, as Appl. No. 16/392,164.
Claims priority of application No. 201910196083.9 (CN), filed on Mar. 15, 2019.
Prior Publication US 2020/0293224 A1, Sep. 17, 2020
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G11C 16/10 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01); G11C 16/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device (100), comprising:
a storage device (110), comprising a plurality of flash memory blocks (112, 114, 116), wherein the flash memory blocks (112, 114, 116) comprises a target block (114), and the target block (114) comprises a plurality of word lines (112, 114, 116) and a plurality of bit lines (134, 135, 136);
a transmission interface (140) arranged to operably receive data to be written into the storage device (110);
a controller circuit (160), comprising:
an access circuit (162) coupled with the storage device (110); and
a flash memory control circuit (164) coupled with the access circuit (162) and the transmission interface (140), and arranged to operably conduct following operations:
controlling the access circuit (162) to write a first data (D1) into one or more pages coupled with a first word line (124) in the target block (114) using a first program scheme at a first time point (T1); and
controlling the access circuit (162) to write a second data (D2) into one or more pages coupled with a second word line (125) in the target block (114) using a second program scheme at a second time point (T2), so as to render both the first data (D1) and the second data (D2) to be present in the target block (114) at the same time, and
a non-volatile storage circuit (150) coupled with the flash memory control circuit (164), storing a word line category record that associates each word line of each memory block with a particular word line category, and each word line category is associated with a data program scheme;
wherein the first program scheme and the second program schemes are different schemes, and wherein the access circuit controls the writing of data into a particularly memory block via the word line that word line category record has associated with data program scheme associated with that data.