US 11,054,890 B2
Distribution of tasks among asymmetric processing elements
Herbert Hum, Portland, OR (US); Eric Sprangle, Portland, OR (US); Doug Carmean, Beaverton, OR (US); and Rajesh Kumar, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 31, 2013, as Appl. No. 13/954,980.
Application 13/954,980 is a continuation of application No. 12/220,092, filed on Jul. 22, 2008, granted, now 8,615,647.
Claims priority of provisional application 61/067,737, filed on Feb. 29, 2008.
Prior Publication US 2013/0318374 A1, Nov. 28, 2013
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/3293 (2019.01); G06F 1/3203 (2019.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01); G06T 1/20 (2006.01); G06F 1/3206 (2019.01); G06F 9/50 (2006.01); G06F 13/24 (2006.01); G06F 9/38 (2018.01); G06F 9/46 (2006.01); G06F 1/3228 (2019.01); G06F 1/20 (2006.01); G06F 1/3287 (2019.01); G06F 12/0875 (2016.01)
CPC G06F 1/3293 (2013.01) [G06F 1/206 (2013.01); G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); G06F 1/3228 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); G06F 9/3869 (2013.01); G06F 9/461 (2013.01); G06F 9/5088 (2013.01); G06F 9/5094 (2013.01); G06F 12/0875 (2013.01); G06F 13/24 (2013.01); G06T 1/20 (2013.01); G06F 2209/5017 (2013.01); G06F 2212/452 (2013.01); Y02B 70/10 (2013.01); Y02B 70/30 (2013.01); Y02D 10/00 (2018.01); Y02D 30/50 (2020.08)] 18 Claims
OG exemplary drawing
1. A processing system comprising:
a graphics processing unit;
a memory controller;
an input-output (I/O) unit;
a processor comprising first and second cores, and a third, low-power core, the first and second cores and the low-power core running concurrently having independent power supplies and clocks and implementing a same instruction set architecture (ISA), the first and second cores to operate at a higher performance level and with higher power consumption than the third, low-power core, wherein the first core runs on a first clock and a first power supply, wherein the second core runs on a second clock and a second power supply, wherein the third core runs on the third clock and a third power supply, wherein the first clock, the second clock, and the third clock are generated from first, second, and third independent clock sources, respectively, and wherein the first, second, and third power supplies are independent from one another in that they originate from different and independent power supply sources; and
software to monitor an activity factor of each of the first and second cores and the third, low-power core, reflecting the activity level of the core as recorded by a plurality of performance counters contained therein and maintaining counts of hardware-related events, wherein the software is internal software of the processor, wherein the software to migrate threads among the first and second cores and the third, low-power core, to optimize performance and power of the processing system without requiring any involvement by an operating system (OS), wherein the OS is an external software of the processor.