US 11,054,884 B2
Using network interface controller (NIC) queue depth for power state management
Brian J. Skerry, Gilbert, AZ (US); Ira Weiny, Livermore, CA (US); Patrick Connor, Beaverton, OR (US); Tsung-Yuan C. Tai, Portland, OR (US); and Alexander W. Min, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 12, 2016, as Appl. No. 15/375,756.
Prior Publication US 2018/0164868 A1, Jun. 14, 2018
Int. Cl. G06F 1/3234 (2019.01); G06F 1/3209 (2019.01); H04L 12/931 (2013.01)
CPC G06F 1/3243 (2013.01) [G06F 1/3209 (2013.01); H04L 49/40 (2013.01); H04L 49/70 (2013.01); Y02D 10/00 (2018.01)] 22 Claims
OG exemplary drawing
 
1. A computer-implemented method, comprising:
processing, by a first central processing unit (CPU) core of a compute device and in a power state equal to a first power state, packets from a first receive queue of a network interface controller (NIC) of the compute device;
receiving a first queue depth for the first receive queue of the NIC;
adjusting, based on the first queue depth, the first power state of the first CPU core to a second power state different from the first power state,
wherein, when the first queue depth is less than a first threshold, adjusting the first power state comprises decreasing the first power state of the first CPU core to the second power state,
wherein, when the first queue depth is greater than a second threshold, adjusting the first power state comprises increasing the first power of the first CPU core to a third power state different from the first power state; and, wherein the method further comprises:
processing, by the first CPU core in the second power state or the third power state, packets from the first receive queue;
receiving a second queue depth for a second receive queue of the NIC; and
adjusting, based on the second queue depth, a fourth power state of the second CPU core to a fifth power state different from the fourth power state.