US 11,054,855 B2
Memory system with multiple channel interfaces and method of operating same
Young-Jin Cho, Seoul (KR); Jae-Geun Park, Suwon-si (KR); Young-Kwang Yoo, Yongin-si (KR); and Soon-Suk Hwang, Ansan-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 2, 2018, as Appl. No. 16/149,987.
Application 16/149,987 is a continuation of application No. 14/995,834, filed on Jan. 14, 2016, granted, now 10,133,298.
Claims priority of application No. 10-2015-0049074 (KR), filed on Apr. 7, 2015.
Prior Publication US 2019/0033909 A1, Jan. 31, 2019
Int. Cl. G06F 1/10 (2006.01); G06F 1/04 (2006.01); G06F 5/06 (2006.01)
CPC G06F 1/10 (2013.01) [G06F 1/04 (2013.01); G06F 5/06 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory controller comprising a master clock generator that generates a master clock and a plurality of channel interfaces disposed in the memory controller and including a first channel interface and a second channel interface;
a plurality of memories including a first memory group and a second memory group; and
a plurality of channels including a first channel connected to the first memory group and a second channel connected to the second memory group,
wherein the first channel interface communicates first signals to the first memory group via the first channel synchronously with a first slave clock and the second channel interface communicates second signals to the second memory group via the second channel synchronously with a second slave clock having a different phase than the first slave clock, and
the first slave clock is derived from a first input clock and the second slave clock is derived from a second input clock, wherein
each one of the first input clock and the second input clock is the master clock as commonly applied to the first channel interface and the second channel interface,
the first channel interface comprises a first clock modulator applying a first modulation to the first input clock, and
the second channel interface comprises a second clock modulator applying a second modulation, different from the first modulation, to the second input clock.