US 11,054,462 B2
Semiconductor device and method of testing the same
Joon Woo Cho, Seoul (KR); Yun Ju Kwon, Yongin-si (KR); and Sang Woo Kim, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 24, 2017, as Appl. No. 15/791,738.
Claims priority of application No. 10-2017-0014217 (KR), filed on Feb. 1, 2017.
Prior Publication US 2018/0217202 A1, Aug. 2, 2018
Int. Cl. G01R 31/28 (2006.01); G06F 1/3206 (2019.01); G06F 1/3209 (2019.01); G06F 1/3296 (2019.01); G06F 1/26 (2006.01)
CPC G01R 31/2853 (2013.01) [G06F 1/26 (2013.01); G06F 1/3206 (2013.01); G06F 1/3209 (2013.01); G06F 1/3296 (2013.01); G01R 31/2884 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a bus configured to transfer signals according to a bus protocol;
a design under test (DUT) electrically connected to the bus;
a processing core electrically connected to the bus and configured to execute test software to determine an operating voltage of the DUT; and
a protection circuit configured to (1) block undefined signals generated by the DUT from being transmitted to the bus while the processing core executes the test software or configured to (2) block transmission of sideband signals generated by the DUT while the processing core executes the test software,
wherein the undefined signals are not defined by the bus protocol, and
wherein the protection circuit is configured to notify the processing core of the generation of the undefined signals or the sideband signals.