US 11,054,461 B1
Test circuits for testing a die stack
Nui Chong, San Jose, CA (US); Amitava Majumdar, San Jose, CA (US); Cheang-Whang Chang, Mountain View, CA (US); Henley Liu, San Jose, CA (US); Myongseob Kim, Pleasanton, CA (US); and Albert Shih-Huai Lin, Mountain View, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Mar. 12, 2019, as Appl. No. 16/351,310.
Int. Cl. G01R 31/28 (2006.01); G01R 31/3185 (2006.01); G01R 31/3177 (2006.01); H01L 25/065 (2006.01)
CPC G01R 31/2851 (2013.01) [G01R 31/3177 (2013.01); G01R 31/318513 (2013.01); H01L 25/0657 (2013.01)] 18 Claims
OG exemplary drawing
1. A device, comprising:
a die stack of two or more integrated circuit dies with associated test circuits corresponding to each level of the die stack, each of the test circuits has a set of pads;
a test data-input path routed from:
a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and
the test data-out pad to the test data-in pad between consecutive levels of the test circuits;
each of the set of pads including the test data-in pad and the test data-out pad respectively thereof;
a test data-output path coupled to the test data-out pad of a level of the levels, wherein the set of pads further comprises a test data-in return pad and a test data-out return pad, and wherein the test data-output path routed from:
the test data-out pad through the test circuit to the test data-out return pad of each of the test circuits; and
the test data-out return pad connected to the test data-in return pad between consecutive ones of the levels of the test circuits.