US 12,349,602 B2
Bottom electrode via and conductive barrier design to eliminate electrical short in memory devices
Chern-Yow Hsu, Chu-Bei (TW); and Shih-Chang Liu, Alian Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 26, 2023, as Appl. No. 18/359,289.
Application 18/359,289 is a division of application No. 17/245,221, filed on Apr. 30, 2021.
Prior Publication US 2023/0371397 A1, Nov. 16, 2023
Int. Cl. H10N 50/80 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01)
CPC H10N 50/80 (2023.02) [H10N 50/01 (2023.02); H10N 50/10 (2023.02)] 20 Claims
OG exemplary drawing
 
8. An integrated chip (IC), comprising:
a first metal interconnect structure disposed within a lower dielectric structure;
a top electrode vertically stacked over a bottom electrode;
a magnetic tunnel junction (MTJ) between the top electrode and the bottom electrode;
a conductive barrier layer disposed over the first metal interconnect structure, wherein the first metal interconnect structure is narrower than the conductive barrier layer;
an etch stop layer arranged over a topmost surface of the conductive barrier layer and along outermost sidewalls of the conductive barrier layer;
a bottom electrode via (BEVA) between the conductive barrier layer and the bottom electrode, wherein a bottommost surface of the bottom electrode continuously extends past opposing outermost sidewalls of the BEVA;
a dielectric layer arranged over the etch stop layer; and
an ILD layer disposed over the lower dielectric structure and laterally surrounding the dielectric layer, wherein the dielectric layer laterally separates the BEVA from the ILD layer and wherein a bottommost surface of the ILD layer is vertically below bottommost surfaces of both the BEVA and the conductive barrier layer.