US 12,349,601 B2
Semiconductor structure and method for manufacturing same, and semiconductor memory
Xiaoguang Wang, Hefei (CN); Huihui Li, Hefei (CN); and Xianqin Hu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, BeiJing (CN)
Filed on Jun. 6, 2022, as Appl. No. 17/832,883.
Application 17/832,883 is a continuation of application No. PCT/CN2021/123606, filed on Oct. 13, 2021.
Claims priority of application No. 202110772837.8 (CN), filed on Jul. 8, 2021.
Prior Publication US 2023/0029195 A1, Jan. 26, 2023
Int. Cl. H01L 43/02 (2006.01); H01L 27/22 (2006.01); H01L 43/12 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10N 50/80 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
providing a Magnetic Random Access Memory (MRAM) cell and an insulating layer, wherein the MRAM cell comprises a bottom electrode, a Magnetic Tunnel Junction (MTJ) stack, and a top electrode, and the insulating layer covers a top surface and a sidewall of the MRAM cell;
sequentially forming and stacking a first dielectric layer, a stop layer, and a second dielectric layer on the insulating layer;
performing a first etching on the second dielectric layer to form a first portion of a top electrode contact hole penetrating through the second dielectric layer and extending to the stop layer; and
performing a second etching on the first dielectric layer and the insulating layer to form a second portion of the top electrode contact hole penetrating through the first dielectric layer and the insulating layer, extending to the top electrode, and deepening the first portion, wherein a radial width of the second portion is gradually decreased with an increase in a depth of the top electrode contact hole;
wherein said forming the first dielectric layer or the second dielectric layer comprises: forming, by using a deposition parameter having a gradient change over time, the first dielectric layer or the second dielectric layer with a characteristic parameter having a gradient change along a depth direction of the top electrode contact hole; or
said performing the second etching on the first dielectric layer and the insulating layer comprises: performing the second etching on the first dielectric layer and the insulating layer by using an etching parameter having a gradient change over time.