US 12,349,599 B2
Memory device having resistance switching layer and integrated circuit device having resistance switching layer
Hsin-Hsiang Tseng, Changhua County (TW); Chih-Lin Wang, Hsinchu County (TW); and Yi-Huang Wu, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Mar. 18, 2024, as Appl. No. 18/608,365.
Application 17/839,326 is a division of application No. 16/721,789, filed on Dec. 19, 2019, granted, now 11,362,267, issued on Jun. 14, 2022.
Application 18/608,365 is a continuation of application No. 17/839,326, filed on Jun. 13, 2022, granted, now 11,963,460.
Prior Publication US 2024/0237545 A1, Jul. 11, 2024
Int. Cl. H10N 50/10 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10N 50/10 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a bottom electrode;
a resistance switching element over the bottom electrode;
a top electrode over the resistance switching element; and
a dielectric layer surrounding the bottom electrode, the resistance switching element, and the top electrode, wherein the resistance switching element has a first portion between the top electrode and the dielectric layer, and a top surface of the dielectric layer is free from coverage by the bottom electrode.