US 12,349,570 B2
Display panel having shielding lines and display device
Qian Ma, Beijing (CN); and Jing Gao, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/786,079
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed May 27, 2021, PCT No. PCT/CN2021/096444
§ 371(c)(1), (2) Date Jun. 16, 2022,
PCT Pub. No. WO2021/239061, PCT Pub. Date Dec. 2, 2021.
Claims priority of application No. 202010470315.8 (CN), filed on May 28, 2020.
Prior Publication US 2023/0028604 A1, Jan. 26, 2023
Int. Cl. H01L 29/08 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/121 (2023.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/131 (2023.02) [H10D 86/441 (2025.01); H10D 86/60 (2025.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/126 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a substrate;
a plurality of pixel driving circuits disposed on the substrate and arranged in an array;
a plurality of first data lines disposed on the substrate, a first data line in the plurality of first data lines being electrically connected to pixel driving circuits in even-numbered rows in a same column of pixel driving circuits;
a plurality of second data lines disposed on the substrate, a second data line in the plurality of second data lines that is arranged adjacent to the first data line being electrically connected to pixel driving circuits in odd-numbered rows in a same column of pixel driving circuits; the first data line and the second data line having an overlapping area therebetween; and
at least one shielding line disposed on the substrate and configured to transmit a fixed voltage, wherein the at least one shielding line constitutes a first capacitor with the first data line, and/or a second capacitor with the second data line;
wherein a parasitic capacitance generated between the first data line and the second data line is less than at least one of a capacitance of the first capacitor or a capacitance of the second capacitor.