US 12,349,482 B2
Backside illumination type solid-state imaging device, manufacturing method for backside illumination type solid-state imaging device, imaging apparatus and electronic equipment
Taizo Takachi, Kanagawa (JP); Yuichi Yamamoto, Kanagawa (JP); Suguru Saito, Kanagawa (JP); Satoru Wakiyama, Kanagawa (JP); Yoichi Ootsuka, Kumamoto (JP); Naoki Komai, Kanagawa (JP); Kaori Takimoto, Kanagawa (JP); Tadashi Iijima, Kanagawa (JP); Masaki Haneda, Kanagawa (JP); and Masaya Nagata, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 16/758,535
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Oct. 16, 2018, PCT No. PCT/JP2018/038423
§ 371(c)(1), (2) Date Apr. 23, 2020,
PCT Pub. No. WO2019/087764, PCT Pub. Date May 9, 2019.
Claims priority of application No. 2017-208864 (JP), filed on Oct. 30, 2017; and application No. 2018-062477 (JP), filed on Mar. 28, 2018.
Prior Publication US 2020/0258924 A1, Aug. 13, 2020
Int. Cl. H10F 39/12 (2025.01); H10F 39/00 (2025.01)
CPC H10F 39/199 (2025.01) [H10F 39/802 (2025.01); H10F 39/811 (2025.01)] 22 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first section including:
a first semiconductor element including a first semiconductor substrate and a first multilayer wiring layer; and
a second section including:
a second semiconductor element including a second semiconductor substrate and a second multilayer wiring layer; and
a third semiconductor element including a third semiconductor substrate and a third multilayer wiring layer,
wherein the first semiconductor element and the second semiconductor element are bonded together such that the first multilayer wiring layer and the second multilayer wiring layer face each other,
wherein the first semiconductor element and the third semiconductor element are bonded together such that the first multilayer wiring layer and the third multilayer wiring layer face each other,
wherein a size of the first semiconductor element is larger than a size of the second semiconductor element and a size of the third semiconductor element,
wherein the size of the second semiconductor element is larger than the size of the third semiconductor element,
wherein a center point of each of the first semiconductor element, the second semiconductor element and the third semiconductor element is aligned,
wherein the first, second, and third multilayer wiring layers include a plurality of terminals,
wherein the plurality of terminals of the first and second multilayer wiring layers are directly bonded,
wherein the plurality of terminals of the first and third multilayer wiring layers are directly bonded, and
wherein the first semiconductor element is disposed between the second and third semiconductor elements.