US 12,349,475 B2
Integrated circuit having vertical routing to bond pads
Eric Miller, Lompoc, CA (US); Christian M. Boemler, Lompoc, CA (US); Justin Gordon Adams Wehner, Goleta, CA (US); Drew Fairbanks, Santa Barbara, CA (US); and Sean P. Kilcoyne, Lompoc, CA (US)
Assigned to Raytheon Company, Arlington, VA (US)
Filed by Raytheon Company, Waltham, MA (US)
Filed on Oct. 25, 2023, as Appl. No. 18/494,163.
Application 18/494,163 is a division of application No. 17/068,223, filed on Oct. 12, 2020, granted, now 11,837,623.
Prior Publication US 2024/0055466 A1, Feb. 15, 2024
Int. Cl. H01L 23/498 (2006.01); H01L 21/311 (2006.01); H01L 23/48 (2006.01); H01L 23/485 (2006.01); H01L 23/488 (2006.01); H10F 39/00 (2025.01); H10F 39/15 (2025.01)
CPC H10F 39/018 (2025.01) [H01L 21/311 (2013.01); H01L 23/481 (2013.01); H01L 23/485 (2013.01); H01L 23/488 (2013.01); H01L 23/49827 (2013.01); H10F 39/024 (2025.01); H10F 39/026 (2025.01); H10F 39/15 (2025.01); H10F 39/805 (2025.01); H10F 39/809 (2025.01); H10F 39/811 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming direct bonding posts on first and second wafers;
depositing oxide layers on direct bonding sides of the first and second wafers; and
directly bonding the first and second wafers at the direct bonding posts to form an assembly;
wherein a direct bonding interface is formed at bonding surfaces of the first and second wafers;
wherein the assembly includes a backside surface and a front side surface;
wherein the first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer;
wherein the second wafer includes vertical routing of the IO signal connections from the first one of the bonding posts on the second wafer to IO pads on the backside surface of the assembly; and
wherein the IO pads are located on a metal layer of the second wafer closest to the backside surface of the assembly.