US 12,349,469 B2
Stack-gate circuit
Yu-Tao Yang, Hsinchu (TW); Wen-Shen Chou, Hsinchu (TW); and Yung-Chow Peng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Nov. 22, 2023, as Appl. No. 18/517,377.
Application 17/723,367 is a division of application No. 16/573,664, filed on Sep. 17, 2019, granted, now 11,309,306, issued on Apr. 19, 2022.
Application 18/517,377 is a continuation of application No. 17/723,367, filed on Apr. 18, 2022, granted, now 12,199,086.
Claims priority of provisional application 62/739,062, filed on Sep. 28, 2018.
Prior Publication US 2024/0088127 A1, Mar. 14, 2024
Int. Cl. H10D 89/10 (2025.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01)
CPC H10D 89/10 (2025.01) [G06F 30/392 (2020.01); G06F 30/394 (2020.01); H10D 84/83 (2025.01); H10D 84/856 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first high-threshold transistor and a first low-threshold transistor having gates thereof conductively connected together, wherein a drain of the first high-threshold transistor is conductively connected to a source of the first low-threshold transistor, and wherein a threshold-voltage of the first high-threshold transistor is larger than a threshold-voltage of the first low-threshold transistor; and
a second high-threshold transistor and a second low-threshold transistor having gates thereof conductively connected together, wherein a drain of the second high-threshold transistor is conductively connected to a source of the second low-threshold transistor, and wherein a threshold-voltage of the second high-threshold transistor is larger than a threshold-voltage of the second low-threshold transistor; and
wherein the gates of the first low-threshold transistor and the second low-threshold transistor are conductively connected to a drain of the first low-threshold transistor.