| CPC H10D 64/258 (2025.01) [H10D 62/80 (2025.01); H10D 64/01 (2025.01); H10D 64/513 (2025.01); H10D 84/83 (2025.01)] | 21 Claims |
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1. A transistor structure, comprising:
a plurality of semiconductor channel layers interleaved with a plurality of gate layers, each of the plurality of gate layers comprising a gate electrode layer between two dielectric layers, wherein the semiconductor channel layers comprise a 2D material;
a source contact on a first lateral end of the semiconductor channel layers and a drain contact on a second lateral end of the semiconductor channel layers opposite the first lateral end;
a plurality of source or drain control electrodes each coplanar with one of the gate electrode layers, laterally between the source or drain contact and the gate electrode layers, and vertically overlapping regions of the semiconductor channel layers and the dielectric layers, the source or drain control electrodes laterally separated from the gate electrode layers by dielectric fill materials;
a gate contact coupled to the gate electrode layers; and
a control gate contact coupled to the source or drain control electrodes.
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