US 12,349,415 B2
Oxide semiconductor transistor
Shunpei Yamazaki, Setagaya (JP); Katsuaki Tochibayashi, Isehara (JP); Ryota Hodo, Atsugi (JP); Kentaro Sugaya, Atsugi (JP); and Naoto Yamade, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jan. 4, 2024, as Appl. No. 18/403,791.
Application 18/403,791 is a continuation of application No. 17/727,038, filed on Apr. 22, 2022, granted, now 11,869,979.
Application 17/727,038 is a continuation of application No. 16/963,928, granted, now 11,316,051, issued on Apr. 26, 2022, previously published as PCT/IB2019/051397, filed on Feb. 21, 2019.
Claims priority of application No. 2018-040286 (JP), filed on Mar. 7, 2018; and application No. 2018-040287 (JP), filed on Mar. 7, 2018.
Prior Publication US 2024/0154039 A1, May 9, 2024
Int. Cl. H01L 29/24 (2006.01); H10B 12/00 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/80 (2025.01)
CPC H10D 30/6755 (2025.01) [H10B 12/05 (2023.02); H10B 12/31 (2023.02); H10D 30/031 (2025.01); H10D 62/80 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a transistor, the transistor comprising:
a first insulator;
a first oxide over the first insulator;
a second oxide over the first oxide;
a second insulator over the second oxide;
a first conductor over the second insulator;
a third insulator in contact with part of a side surface of the second oxide, part of a side surface of the first oxide, and part of the first insulator;
a fourth insulator over the third insulator; and
a fifth insulator in contact with a top surface of the second insulator, a top surface of the first conductor, and a top surface of the fourth insulator,
wherein the second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region,
wherein resistance of the first region and resistance of the second region are lower than resistance of the third region,
wherein the first conductor is provided above the third region to overlap with the third region,
wherein part of the second insulator is provided between a side surface of the first conductor and a side surface of the fourth insulator,
wherein the third insulator comprises a region in contact with the first region and a region in contact with the second region, and
wherein in a channel width direction of the transistor, a height of a bottom surface of the first conductor in a region where the first conductor and the second oxide do not overlap with each other is lower than a height of a bottom surface of the second oxide.