| CPC H10D 30/6735 (2025.01) [H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 62/83 (2025.01); H10D 64/01 (2025.01); H10D 64/258 (2025.01); H10D 64/62 (2025.01)] | 20 Claims |
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1. A device, comprising:
a substrate;
a channel region of a transistor overlying the substrate;
a source/drain region in contact with the channel region, the source/drain region adjacent to the channel region along a first direction;
a source/drain contact on the source/drain region;
a dielectric liner layer lining a sidewall of the source/drain contact;
a gate electrode on the channel region;
a gate dielectric layer on the gate electrode;
a gate contact on the gate electrode;
a gate spacer dielectric layer between the gate electrode and the dielectric liner layer; and
a first dielectric layer in contact with a top surface of the gate spacer dielectric layer, in contact with the dielectric liner layer above the gate spacer dielectric layer, and in contact with a sidewall of the gate contact.
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