| CPC H10D 30/6713 (2025.01) [H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0184 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a substrate;
an active pattern on the substrate, wherein the active pattern extends in a first direction;
a device isolation layer provided on the substrate to define the active pattern;
a pair of source/drain patterns on the active pattern and a channel pattern therebetween, the channel pattern comprising semiconductor patterns which are stacked and are spaced apart from each other;
a gate electrode crossing the channel pattern, wherein the gate electrode extends in a second direction crossing the first direction; and
a gate spacer on a side surface of the gate electrode,
wherein the gate spacer located on the device isolation layer comprises an upper portion with a first thickness in the first direction and a lower portion with a second thickness in the first direction,
wherein the second thickness is larger than the first thickness,
wherein the lower portion of the gate spacer comprises a first insulating layer, a second insulating layer, and a third insulating layer which overlap each other in the first direction, the second insulating layer being between the first insulating layer and the third insulating layer,
wherein the upper portion of the gate spacer comprises the first insulating layer and the third insulating layer which overlap each other in the first direction, and
wherein the lower portion of the gate spacer is located at a level lower than an uppermost one of the semiconductor patterns.
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