| CPC H10D 30/024 (2025.01) [H10D 30/6211 (2025.01); H10D 62/115 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A semiconductor structure, comprising:
a substrate;
a base fin rising from the substrate;
a first isolation feature portion and a second isolation feature portion over the substrate and sandwiching the base fin;
a first dielectric structure disposed on the first isolation feature portion;
a second dielectric structure disposed on the second isolation feature portion;
a plurality of channel members disposed over the base fin and between the first dielectric structure and the second dielectric structure; and
a gate structure disposed between the first dielectric structure and the second dielectric structure and wrapping around each of the plurality of channel members,
wherein each of the first dielectric structure and the second dielectric structure comprises a base feature and a mask feature over the base feature,
wherein the mask feature comprises a bottom width and a top width greater than the bottom width such that the mask feature tapers downward.
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