| CPC H10D 30/024 (2025.01) [H10D 30/014 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 30/6735 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 64/018 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
a first nanostructure and a second nanostructure overlying a fin over a semiconductor substrate;
an isolation region adjacent the fin;
a first inner spacer located between the first nanostructure and the semiconductor substrate;
a first spacer material in contact with the first inner spacer;
a first source/drain region over an upper surface of the first spacer material, wherein the first source/drain region contacts both the first spacer material and the first inner spacer;
a first gate electrode surrounding the first nanostructure and the second nanostructure;
a second gate electrode adjacent the first gate electrode and having a longitudinal axis parallel to a longitudinal axis of the first gate electrode; and
a dielectric structure extending through the second gate electrode and into the fin, a bottommost surface of the dielectric structure being above a bottom of the first spacer material, the dielectric structure comprising:
a first layer having a bottom surface on a top surface of the isolation region; and
a second layer adjacent the first layer, the second layer extending into the fin.
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