US 12,349,368 B2
Memory device including a semiconducting metal oxide fin transistor and methods of forming the same
Yong-Jie Wu, Hsinchu (TW); Yen-Chung Ho, Hsinchu (TW); Hui-Hsien Wei, Taoyuan (TW); Chia-Jung Yu, Hsinchu (TW); Pin-Cheng Hsu, Zhubei (TW); Mauricio Manfrini, Zhubei (TW); and Chung-Te Lin, Taiwan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,460.
Application 18/358,460 is a division of application No. 17/229,753, filed on Apr. 13, 2021, granted, now 12,058,873.
Claims priority of provisional application 63/045,289, filed on Jun. 29, 2020.
Prior Publication US 2023/0371278 A1, Nov. 16, 2023
Int. Cl. H10B 61/00 (2023.01); H01L 21/02 (2006.01); H10B 53/30 (2023.01); H10B 63/00 (2023.01); H10D 30/62 (2025.01); H10D 62/80 (2025.01); H10D 99/00 (2025.01); H10N 50/01 (2023.01); H10N 70/00 (2023.01)
CPC H10B 61/22 (2023.02) [H01L 21/02565 (2013.01); H10B 53/30 (2023.02); H10B 63/30 (2023.02); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 62/80 (2025.01); H10D 99/00 (2025.01); H10N 50/01 (2023.02); H10N 70/011 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a semiconducting metal oxide fin over a top surface of at least one lower-level dielectric material layer;
forming a gate dielectric layer over the semiconducting metal oxide fin;
forming a gate electrode strip across the semiconducting metal oxide fin over the gate dielectric layer;
forming an auxiliary source line over the gate dielectric layer;
forming a source region and drain region in the semiconducting metal oxide fin by performing an ion implantation process that implants electrical dopants which induce formation of excess electrons or holes into unmasked portions of the semiconducting metal oxide fin employing the gate electrode strip an ion implantation mask;
forming an access-level dielectric material layer over the gate electrode strip and the semiconducting metal oxide fin;
forming a source contact via structure through the access-level dielectric material layer on a top surface of the source region within the semiconducting metal oxide fin;
forming a source connection via structure through the access-level dielectric material layer on a top surface of the auxiliary source line;
forming a source line on a top surface of the source contact via structure and on a top surface of the source connection via structure, wherein the source line is electrically connected to the auxiliary source line through the source connection via structure; and
forming a memory cell within a memory-level dielectric material layer over the access-level dielectric material layer.