US 12,349,367 B2
Semiconductor device and method for fabricating the same
Chih-Wei Kuo, Tainan (TW); Tai-Cheng Hou, Tainan (TW); Yu-Tsung Lai, Tainan (TW); and Jiunn-Hsiung Liao, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Sep. 5, 2023, as Appl. No. 18/242,014.
Application 17/336,295 is a division of application No. 16/544,923, filed on Aug. 20, 2019, granted, now 11,056,536, issued on Jul. 6, 2021.
Application 18/242,014 is a continuation of application No. 17/336,295, filed on Jun. 1, 2021, granted, now 11,785,785.
Claims priority of application No. 108125208 (TW), filed on Jul. 17, 2019.
Prior Publication US 2023/0413579 A1, Dec. 21, 2023
Int. Cl. H10N 50/80 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01)
CPC H10B 61/22 (2023.02) [H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate;
a first top electrode on the first MTJ and a second top electrode on the second MTJ;
a first spacer and a second spacer around the first MTJ, wherein top surfaces of the first spacer, the second spacer, and the first top electrode are coplanar;
a third spacer and a fourth spacer around the second MTJ;
a passivation layer between the second spacer and the third spacer and filling a space between the first MTJ and the second MTJ completely, wherein a top surface of the passivation layer comprises a V-shape surface, and the V-shape surface directly connecting and extending from the top surface of the first spacer; and
an ultra low-k (ULK) dielectric layer on the passivation layer and around the first MTJ and the second MTJ.