US 12,349,364 B1
Memory structures and methods of forming the same
Kian Hui Goh, Singapore (SG); Xinshu Cai, Singapore (SG); and Shyue Seng Tan, Singapore (SG)
Assigned to GlobalFoundries Singapore Pte. Ltd., Singapore (SG)
Filed by GlobalFoundries Singapore Pte. Ltd., Singapore (SG)
Filed on Jul. 29, 2024, as Appl. No. 18/786,636.
Int. Cl. H10B 51/30 (2023.01); G11C 11/14 (2006.01); G11C 11/16 (2006.01); G11C 11/22 (2006.01); H01L 21/02 (2006.01)
CPC H10B 51/30 (2023.02) [G11C 11/14 (2013.01); G11C 11/16 (2013.01); G11C 11/161 (2013.01); G11C 11/22 (2013.01); G11C 11/221 (2013.01); G11C 11/223 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure for a non-volatile memory device, comprising:
a semiconductor layer having a body region of a first conductivity type;
a first electrode including a doped region of a second conductivity type in the semiconductor layer, the doped region is adjacent to the body region, the doped region comprises a first portion and a second portion extending laterally from the first portion, wherein the first portion has a first width and the second portion has a second width, the first width is greater than the second width;
a ferroelectric layer on the semiconductor layer over the body region; and
a second electrode on the ferroelectric layer, wherein the first portion and the second portion of the doped region partially underlap the second electrode, and a first side surface of the first portion and a first side surface of the second portion of the doped region does not underlap the second electrode.