US 12,349,362 B2
High selectivity isolation structure for improving effectiveness of 3D memory fabrication
Tsu Ching Yang, Taipei (TW); Feng-Cheng Yang, Zhudong Township (TW); Sheng-Chih Lai, Hsinchu County (TW); Yu-Wei Jiang, Hsinchu (TW); Kuo-Chang Chiang, Hsinchu (TW); Hung-Chang Sun, Kaohsiung (TW); Chen-Jun Wu, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 14, 2023, as Appl. No. 18/334,590.
Application 18/334,590 is a division of application No. 17/333,300, filed on May 28, 2021, granted, now 11,723,210.
Claims priority of provisional application 63/157,217, filed on Mar. 5, 2021.
Prior Publication US 2023/0328996 A1, Oct. 12, 2023
Int. Cl. H10B 51/20 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a semiconductor substrate;
a word line stack, wherein the word line stack comprises a word line and an insulating layer alternatingly stacked over the semiconductor substrate, wherein the word line stack extends in a first direction;
a ferroelectric data storage layer extending in the first direction along a sidewall of the word line stack;
a channel layer extending in the first direction, disposed along a sidewall of the ferroelectric data storage layer;
a pair of source/drain regions disposed along sides of the channel layer, the pair of source/drain regions separated from one another by an insulating structure made of a first dielectric material along the first direction; and
an isolation structure disposed on ends of the channel layer and arranged along the sidewall of the ferroelectric data storage layer, wherein the isolation structure comprises a second dielectric material different from the first dielectric material.