US 12,349,356 B2
Semiconductor memory device that includes a semiconductor column that penetrates a plurality of conductive layers
Toshifumi Hashimoto, Fujisawa (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Nov. 7, 2023, as Appl. No. 18/503,233.
Application 18/503,233 is a division of application No. 17/181,027, filed on Feb. 22, 2021, granted, now 11,856,774.
Claims priority of application No. 2020-136487 (JP), filed on Aug. 12, 2020.
Prior Publication US 2024/0081065 A1, Mar. 7, 2024
Int. Cl. H10B 43/27 (2023.01); H01L 23/00 (2006.01); H10B 43/10 (2023.01); H10D 30/69 (2025.01)
CPC H10B 43/27 (2023.02) [H01L 24/46 (2013.01); H10B 43/10 (2023.02); H10D 30/69 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a substrate;
a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, the plurality of first conductive layers extending in a second direction intersecting with the first direction;
a second conductive layer arranged with the plurality of first conductive layers in the first direction, the second conductive layer extending in the second direction, the second conductive layer disposed at a position farther from the substrate than the plurality of first conductive layers or a position closer to the substrate than the plurality of first conductive layers;
a third conductive layer arranged with the plurality of first conductive layers in the first direction, the third conductive layer arranged with the second conductive layer in the second direction, the third conductive layer extending in the second direction;
a first semiconductor column extending in the first direction, the first semiconductor column penetrating the plurality of first conductive layers and the second conductive layer;
a second semiconductor column extending in the first direction, the second semiconductor column penetrating the plurality of first conductive layers and the third conductive layer;
a first electric charge accumulating film disposed between the plurality of first conductive layers and the first semiconductor column;
a second electric charge accumulating film disposed between the plurality of first conductive layers and the second semiconductor column;
a first wiring extending in the second direction, the first wiring disposed at a position farther from the plurality of first conductive layers than the second conductive layer and the third conductive layer;
a first contact disposed between an end portion in the second direction of the second conductive layer and the first semiconductor column, the first contact electrically connected to the second conductive layer and the first wiring;
a second contact disposed between an end portion in the second direction of the third conductive layer and the second semiconductor column, the second contact electrically connected to the third conductive layer and the first wiring;
a second wiring extending in a third direction intersecting with the first direction and the second direction, the second wiring electrically connected to the first semiconductor column; and
a third wiring extending in the third direction, the third wiring electrically connected to the second semiconductor column,
wherein the second wiring is disposed between the second conductive layer and the first wiring, and
wherein the third wiring is disposed between the third conductive layer and the first wiring.