| CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02)] | 2 Claims |

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1. A memory device, comprising:
at least one alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the at least one alternating stack; and
a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel,
wherein:
the memory opening fill structure comprises a lateral protrusion having a tapered sidewall surface; and
one of the electrically conductive layers of the at least one alternating stack comprises a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening fill structure;
wherein the taper-containing electrically conductive layer comprises a contoured sidewall having a tapered sidewall segment that is parallel to the tapered sidewall surface of the lateral protrusion;
wherein the tapered sidewall segment is an annular tapered sidewall segment having an inner periphery that is vertically offset from an outer periphery by a vertical offset distance;
wherein the contoured sidewall comprises a first vertical straight cylindrical sidewall segment that is adjoined to the outer periphery of the annular tapered sidewall segment; and
wherein the contoured sidewall further comprises a second vertical straight cylindrical sidewall segment that is adjoined to the inner periphery of the annular tapered sidewall segment.
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