| CPC H10B 43/27 (2023.02) [G11C 16/10 (2013.01); G11C 16/26 (2013.01)] | 20 Claims |
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1. A memory device comprising:
interlayer insulating layers and conductive layers stacked alternately with each other;
a vertical hole passing through the alternately stacked conductive layers and interlayer insulating layers;
first blocking layers formed along the interlayer insulating layers exposed through the vertical hole;
second blocking layers formed along the conductive layers exposed through the vertical hole, wherein each of the second blocking layers has a thickness greater than a thickness of each of the first blocking layers;
charge trap layers formed on the same layer as the interlayer insulating layers, and surrounded by the first and second blocking layers, wherein the charge trap layers are separated from each other along a direction in which the first and second blocking layers are stacked;
a tunnel insulating layer formed along inner walls of the second blocking layers and the charge trap layers; and
a channel layer formed along an inner wall of the tunnel insulating layer, wherein the charge trap layers are not located on the same layer as the conductive layers; and
wherein layers that store data are not located on the same layer as the conductive layers.
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