| CPC H10B 43/27 (2023.02) [H01L 23/562 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a peripheral circuit structure including a peripheral transistor;
a semiconductor layer on the peripheral circuit structure;
a source structure on the semiconductor layer;
a gate stack structure on the source structure, the gate stack structure including insulating patterns and conductive patterns alternately stacked;
a memory channel structure penetrating the gate stack structure, the memory channel structure being electrically connected to the source structure;
a support structure penetrating the gate stack structure and the source structure, the support structure including:
an outer support layer in contact with side walls of the insulating patterns and side walls of the conductive patterns, and
a support pattern and an inner support layer in contact with an inner side wall of the outer support layer; and
an insulating layer covering the gate stack structure, the memory channel structure, and the support structure,
wherein a top surface of the outer support layer, a top surface of the inner support layer, and a top surface of the support pattern being in contact with a bottom surface of the insulating layer.
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