US 12,349,342 B2
Semiconductor structure and method for manufacturing same, memory and operation method thereof
Yanzhe Tang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 30, 2022, as Appl. No. 17/899,145.
Application 17/899,145 is a continuation of application No. PCT/CN2022/103663, filed on Jul. 4, 2022.
Claims priority of application No. 202210728734.6 (CN), filed on Jun. 24, 2022.
Prior Publication US 2023/0422492 A1, Dec. 28, 2023
Int. Cl. H10B 20/25 (2023.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01)
CPC H10B 20/25 (2023.02) [G11C 17/16 (2013.01); G11C 17/18 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate having a plurality of active areas close to a surface of the substrate;
a gate structure located in a first structure layer on the substrate, the gate structure and the active areas forming a selective transistor; and
an anti-fuse bit structure located in a second structure layer on the first structure layer, and being connected with an active area of one selective transistor through a first connecting structure, a breakdown state and a non-breakdown state of the anti-fuse bit structure representing different stored data; and
wherein the anti-fuse bit structure comprises:
a first electrode connected to the active area through the first connecting structure;
a second electrode located in a same plane with the first electrode, the plane where the first electrode and the second electrode are located being parallel to the surface of the substrate; and
an anti-fuse bit dielectric layer located between the first electrode and the second electrode and connected with the first electrode and the second electrode, wherein the breakdown state is a state in which the anti-fuse bit dielectric layer is broken down, and the non-breakdown state is a state in which the anti-fuse bit dielectric layer is not broken down.